Techniques for Aggressive Supply Voltage Scaling and Efficient Regulation

Aggressive voltage scaling to 1 V and below through technology, circuit, and architecture optimization is the key to low-power design. Threshold voltage scaling enables aggressive supply scaling but increases leakage power. Technology and circuit trends to control idle leakage power are presented including MTCMOS, variable VT bulk-CMOS, and variable VT Sol . Power can also be reduced by adaptively varying the supply voltage in applications where the computational workload varies with time. Aggressive voltage and power level scaling requires efficient DC-DC conversion circuitry and in some cases, it is necessary to embed this function in the processor. 1. Analysis of Power Components There are three main sources of power consumption in digital CMOS circuits: switching power, short circuit power, and leakage power. In conventional process technology, the switching component dominates and is given by a*CL. VDo *AV.fclkwhere a is the node transition activity factor, CL is load capacitance, VDD is the supply voltage, AV is the voltage swing, and fclk is the clock frequency. The activity factor (a) is a strong function of signal statistics and circuit topology. A variety of techniques have been proposed to reduce switching activity ranging from low level logic restructuring and power down techniques, to architectural restructuring and selection of data representation [ l ] . It is important to consider transitions that are fundamentally required to perform a given operation as well as spurious transitions arising from imbalances in the signal path. Various approaches have been proposed to reduce glitching transitions in arithmetic structures by balancing signal paths (e.g., [2]). In conventional CMOS logic with rail-to-rail swing, the most efficient approach to lower energy consumption is to operate at the lowest possible power supply voltage. The individual circuit elements, however, run slower at lower supply voltages and circuit performance degrades. One approach to maintain throughput at reduced voltages is to use parallel architectures to compensate for increased gate delays [l 1. Significant power reduction over conventional approaches is possible at the cost of increased silicon area. A variety of voltage scaling strategies are described here which reduce power without significantly increasing silicon area. Associated with aggressive voltage and power scaling is the need for high-efficiency regulation techniques. In many cases, embedding the power converter control in the processor can significantly reduce power dissipation. The switching power can also be reduced at a fixed supply voltage by using low-swing signalling. One approach involves reducing the swing on high capacitance nodes using reference voltages generated on-chip [3]. Charge kharing techniques can also be used significantly reduce the voltage swing on data busses 141. The short-circuit component arises when both the NMOS and PMOS transistors are “ON” simultaneously, providing a direct path from VDD to ground. By sizing transistors such that the input and output rise-times are approximately equal, the short circuit component can be kept to less than 10% of the total power [5]. Leakage power results from reverse biased diode conduction and subthreshold operation. The sub-threshold leakage occurs due to carrier diffusion when the gatesource voltage, V&, has exceeded the weak inversion point, but is still below the threshold voltage V , where carrier drift is dominant. In this regime, the current is exponentially dependent on the gate-source voltage VGs. Scaling supply voltages below 1V requires the scaling of the threshold voltage, which unfortunately comes at the cost of increased leakage (Figure 1). While leakage is typically negligible when circuits are active, it can be significant during idle mode. A variety of technology and circuit solutions are discussed here which address the conflicting requirements of high-performance during O l l 0:2 0:3 Of4 015 0:6 0:7 018 019 l!O VG.5 fv. Figure 1. Subthreshold leakage in MOS. 0-7803-3669-0 $5.00